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Patent Searching and Data


Title:
INVERSION DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5842354
Kind Code:
A
Abstract:

PURPOSE: To make large scale integration easy without the use of resistive and capacitive elements, by constituting all of polarity inverting circuits of a telephone line with logical elements.

CONSTITUTION: The 1st and 2nd line control signals LC1 and LC2 are respectively inputted to FF1 and FF4, the output of the FF1 is applied to an AND gate 7 via FFs 2 and 3 and the output of the FF4 is applied to an AND gate 9 via FFs 5 and 6. Further, the output of the FFs 1, 4 is applied to gates 9 and 7 respectively and inverted at inverters 8, 10 and applied to the gates 7 and 9. The output of the gates 7, 9 is applied to an OR gate 11, where logical sum is taken. The output of the gate 11 is applied to an OR gate 14 via an FF12 and to the gate 14 via an inverter 13 and the inversion is detected once at the gate 14, the inverter 13 and the FF12. All the polarity inversion circuits are constituted with logical elements, allowing to make large scale circuit integration easy without the use of resistive and capacitive elements.


Inventors:
HIRAI SEIICHI
NAKAYAMA YASUNOBU
Application Number:
JP14076181A
Publication Date:
March 11, 1983
Filing Date:
September 07, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H04M11/00; H04M1/00; H04M1/82; H04M15/00; H04M15/28; H04M15/30; (IPC1-7): H04M1/00; H04M11/00; H04M15/28
Attorney, Agent or Firm:
Takehiko Suzue