Title:
PICTURE PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JPS5983266
Kind Code:
A
Abstract:
PURPOSE:To control dynamically the number of stages of a pipeline and make the delay time constant, by outputting the output from an arithmetic device, which processes an input video through a selecting circuit in a pipeline picture processing circuit. CONSTITUTION:A video signal 13 of a TV camera 1 is made binary by a binary circuit 2, and a video signal 14 is outputted. The signal 14 is inputted to a fundamental circuit 3, and a prescribed arithmetic result or the inputted video signal is selected by a selecting signal 9 to output signal 15. The signal 15 becomes an input signal of a fundamental circuit 4 of the next stage. Consequently, the number of stages is controlled practically with respect to an output 16 of the final stage. Normally, a reduced pattern has a delay time corresponding to the number of stages of fundamental circuits 3-5; and therefore, even if the number of stages of the pipeline is changed dynamically, the delay time of the output result of the final stage is always constant, and succeeding processings are facilitated.
Inventors:
MIYATAKE TAKAFUMI
UEDA HIROTADA
MATSUSHIMA HITOSHI
KASHIOKA SEIJI
EJIRI MASAKAZU
UEDA HIROTADA
MATSUSHIMA HITOSHI
KASHIOKA SEIJI
EJIRI MASAKAZU
Application Number:
JP19340682A
Publication Date:
May 14, 1984
Filing Date:
November 05, 1982
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06T1/20; (IPC1-7): G06F15/20; G06F15/31
Attorney, Agent or Firm:
Toshiyuki Usuda