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Patent Searching and Data


Title:
METHOD FOR TESTING IC MEMORY
Document Type and Number:
Japanese Patent JPS5930072
Kind Code:
A
Abstract:

PURPOSE: To make it possible to easily discover error operation caused by a skew without increasing the number of test processes, by applying an arbitrary synchronous skew including all combinations between mutual input signals from a tester.

CONSTITUTION: Eight signals from each output terminals of FF4 are reset by a clock signals 3a to be successively converted to a delay signal group one cycle or a plurality of cycles late by the oscillation frequency of OSC5 and respectively sent out to the MPX7 in parallel. On the other hand, if eight sets of figure lines comprising arbitrary three bit cominations are constituted from total 24 bits obtained from six four-bit counter 6, a variable different in content is obtained at every one clock signal 3a to be sent out as the selection signal of MPX7. Each FF8 sends out new address information AW7 applied with a skew in timing according to the delay signal selected by MPX7 corresponding at every one cycle. By this method, all combinations among eight kinds are written in and can be provided in an indefinite order in reading operation.


Inventors:
OOE GIICHI
Application Number:
JP14031282A
Publication Date:
February 17, 1984
Filing Date:
August 12, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R31/3193; G01R31/28; G11C29/00; G11C29/50; G11C29/56; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Sadaichi Igita