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Patent Searching and Data


Title:
EQUALIZING CIRCUIT
Document Type and Number:
Japanese Patent JPS5910037
Kind Code:
A
Abstract:

PURPOSE: To compensate smoothly a ripple, etc. produced to the frequency characteristics, by branching a part of an input signal, inverting the output polarity of a delay circuit and synthesizing the inverted output with the input signal.

CONSTITUTION: An input electric signal e2 is branched by a branching circuit 4 and reaches an inverting circuit 6 via a delay circuit 5. A signal of adverse polarity to the signal e2 of the output of the circuit 6 is added with the signal e2 at a synthesizing circuit 7 and turned into an output signal e3. If the delay time of the circuit 5 is set double as much as a transmission delay circuit for optical fiber transmission line, the signal e3 contains a component opposite to the ripples produced by reflection with the same frequency intervals as the ripples. Then the level is properly set for the delayed signal after synthesization, and therefore the deterioration can be reduced for the desired frequency characteristics. The delay time is set by a delay circuit 9 with tap, and the circuit 6 inverts the polarity through a transformer. The circuit 7 varies a variable attenuator 11 to set the quantity of a delay signal component contained in the signal e3.


Inventors:
MATSUHASHI MASAMICHI
YASUKI TOSHIHARU
Application Number:
JP11883782A
Publication Date:
January 19, 1984
Filing Date:
July 07, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03H7/01; H04B3/04; H04B3/14; H04B10/2507; (IPC1-7): H03H7/01; H04B3/04; H04B9/00
Attorney, Agent or Firm:
Naotaka Ide