Title:
MASTER SLICE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5864047
Kind Code:
A
Abstract:
PURPOSE:To construct a logic circuit and a memory circuit without decreasing their cell utility rate by forming a set of transistors and at least two first conductive type transistors at the center and a complementary transistor. CONSTITUTION:The gate polysilicon 8 of two PMOS transistors connected in series via a P<+> type source and drain layer 6, the gate polysilicon 5 of four NMOS transistors connected in series via N<+> type source and drain layer 3, gate polysilicons 5, 8, and contacting holes 10 of the layers 6, 3 are formed on an N type silicon substrate 1. The gate polysilicon 5A becomes the gate of TG1, the gate polysilicon 5D becomes the gate of TG2, the gate polysilicons 5B, 8A become IB, and the gate polysilicons 5C, 8B become IA. Thus, the cell utility rate in case of forming a memory becomes 100%, two gate polysilicons 5 of the right and left end NMOST are added, but no trouble occurs in the construction of a logic circuit.
Inventors:
FUJIKI KUNIMITSU
Application Number:
JP16300581A
Publication Date:
April 16, 1983
Filing Date:
October 13, 1981
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/822; H01L21/82; H01L27/04; H01L27/10; H01L27/118; (IPC1-7): H01L21/82; H01L27/04; H01L27/10
Domestic Patent References:
| JPS57211248A | 1982-12-25 |
Attorney, Agent or Firm:
Uchihara Shin
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