Title:
INSPECTING SYSTEM
Document Type and Number:
Japanese Patent JPS5831549
Kind Code:
A
Abstract:
PURPOSE:To enable an inspecting system which can efficiently operate an inspecting facility by prenotifying the ending time of a testing work. CONSTITUTION:Wafer probes 2, 2' test by a testing unit 1 chips on a wafer, and when all chips are completely tested, a test end signal of one wafer is fed to a processor 3. The processor 3 reads out by a clock 4 a time of receiving the signal, and obtains a difference from the time of the previous test end signal, i.e., the testing time of one wafer. When the testing times of the wafers of the previously arbitrarily specified number are obtained, the mean testing time of one wafer can be decided. The processor 3 decides the planed test end time of the lot is estimated from the obtained mean testing time and indicates it on an indicator 6. When the time before the arbitrarily set prescribed time of the planted time comes, the finish of the test of this lot after the prescribed time is indicated on the indicator 6. The finishing time is prenotified by applying a simple device.
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Inventors:
MATSUKAWA YASUSHI
Application Number:
JP12967581A
Publication Date:
February 24, 1983
Filing Date:
August 19, 1981
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G01R31/26; G01R31/28; H01L21/66; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Shin Uchihara