PURPOSE: To easily design plural on-chip memories different from each other in bit numbers constituting one word, by combining the appropriate number of blocks and constituting a memory having a desired size.

CONSTITUTION: When address signals A0WA5 are inputted into an X-address buffer, X-ADB, one line out of the 64 word lines in each memory cell block B0W B3 is set to the selection level by an X-decoder X-DEC. Furthermore, when address signals A6WA9 of Y-address buffer Y-ADB of blocks C and C are inputted, Y-decoders Y-DEC in each memory cell block B0WB3 are simultaneously operated and one line out of data lines in each memory cell array MAR is selected. As a result, 1-bit data are outputted from the sense amplifier SA of each memory cell block B0WB3 and totally 4-bit data are read out in parallel.