PURPOSE: To reduce the capacity required for an address conversion RAM by dividing display addresses into horizontal and vertical directions and connecting horizontal and vertical display address conversion RAMs to each display address bus so as to apply conversion processing to the horizontal and vertical display addresses.

CONSTITUTION: The system is provided with a horizontal display address counter 2 receiving a display clock from a display clock generating circuit 1 and outputting a horizontal display address, a vertical display address counter 3 outputting a vertical display address, a horizontal display address conversion RAM 6 whose address input receives a horizontal display address, a vertical display address conversion RAM 7 whose address input receives a vertical display address, a picture memory 10, a D/A converter 11 converting a picture data read from the picture memory 10 into a video signal and sending the video signal to a display device and a microcomputer 12 controlling the changeover of changeover devices 4, 5, 8, 9 to switch the data in the RAMs 6, 7. Thus, the capacity required for an address conversion RAM is reduced.