PURPOSE: To reduce the test time, by performing set/reset operation with a signal by-passing the prestage logic at the through-mode and performing the operation with a signal from the prestage logic at the normal mode, by using control pins, a decoder and gates.

CONSTITUTION: A pattern "00" is set to a register 6 from control pins 6. A control line 8 is set to "1" and lines 9, 10 are set to "0" by a decoder 7, only an LSI2 is the normal mode and LSIs 3, 4 are the through-mode, allowing to check failures at the inside of the LSIs. In the production of the test pattern for the purpose, when the by-pass signal for the LSIs 3, 4 and the logical block of the LSI2, and a switch is used for a switch gate, the LSI3 or 4 are used, the test pattern of the LSI2 is used and the rate of detection almost equal to the single LSI2 is obtained. Similarly, a check is performed for the LSIs 3, 4 by resetting addresses with the control pins 5.