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Title:
SEMICONDUCTOR CIRCUIT
Document Type and Number:
Japanese Patent JPS5912630
Kind Code:
A
Abstract:

PURPOSE: To obtain an inverter circuit where the amplification of a signal is stable to discriminate an external signal input and the attenuation in an output signal is less, by generating a couple of different one-shot voltages in response to the external input to assist the amplification of signal of the inverter circuit.

CONSTITUTION: A level of an external input voltage VIN and a Vref is latched respectively to source nodes N9 and N10 by EMOSTsT17 and T18 designating a signal P as a gate input when the latch signal P is brought from a high level to a low level. On the other hand, two one-shot voltages having different peak voltage due to the voltage difference between the two inputs are generated in a one-shot generating circuit. Further, two one-shot votages having the different peak voltage are inputted to one end of capacitors C3, C4, the one-shot voltage having the higher peak voltage is inputted to the node having a higher voltage between the nodes N9 and N10 of the other end and the one-shot voltage having the lower peak voltage is inputted to the node having the lower voltage, respectively, allowing to assist the signal voltage of the inverter.


Inventors:
HOSHI KATSUSHI
Application Number:
JP12159682A
Publication Date:
January 23, 1984
Filing Date:
July 13, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K19/096; (IPC1-7): H03K19/096
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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