PURPOSE: To shorten an instruction executing time, by eliminating ineffective arithmetic executing cycles when composite operation is executed.

CONSTITUTION: A vector instruction controlling circuit 5 decides whether or not an instruction word 100 is a vector instruction and outputs a switching signal 101 to a selector 17 in accordance with the decided result and, at the same time, an arithmetic designating signal 102 which designates an instruction code and operand to an arithmetic designating circuit 9. The circuit 5 outputs a timing signal 103 to the 1st and 2nd operand buffers 2 and 3 and a constant memory 4 correspondingly to the kind of the instruction designated by the instruction code and causes the buffers 2 and 3 and memory 4 to output their holding data V1, V2 and C. The circuit 9 outputs an operation controlling signal 104 to the selector 17 in accordance with the values of the signal 102 and each output data V1, V2 and C and a switching signal 105 to selectors 15 and 16. An arithmetic controlling circuit 12 outputs an operation executing signal 106 to a multiplier/ divider circuit 10, adder/subtractor circuit 11, and selector 18 in response to the arithmetic controlling signal 104.