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Title:
LOGIC ANALYZER
Document Type and Number:
Japanese Patent JPS6035273
Kind Code:
A
Abstract:

PURPOSE: To convert input data into a corresponding sign set to indicate by providing an input signal memory means, a means of setting a sign corresponding to the value of the input signal and a means of recognizing the correspondence of the memory contents to the input signal and replacing the signal value recognized with a corresponding signal.

CONSTITUTION: The main program 2 and the related subprogram 3 operate in cooperation with a data structure 4 named "DATA-BLOCK". The name of the main program is "MAIN" and the name of the subprogram "FACTOR". In conjunction with these two PASCAL programs and the data structure thereof, three utility programs are made available from a library in execution to be called with a compiler of PASCAL while the programs MAIN and FACTOR are being compiled. They are a parameter passage routine 5, a multiplication routine 6 and a check routine 7.


Inventors:
BURIISU ESU GUTSUDOUIN JIYUNIA
Application Number:
JP6313584A
Publication Date:
February 23, 1985
Filing Date:
March 30, 1984
Export Citation:
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Assignee:
HEWLETT PACKARD YOKOGAWA
International Classes:
G01R13/28; G01R13/20; G06F11/28; (IPC1-7): G01R13/20
Domestic Patent References:
JPS5445179A1979-04-10
JPS5561867A1980-05-09
Attorney, Agent or Firm:
Hasegawa Tsugio