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Patent Searching and Data


Title:
DIGITAL TELEVISION RECEIVER
Document Type and Number:
Japanese Patent JPS5923985
Kind Code:
A
Abstract:

PURPOSE: To obtain a voltage for pedestal lamp, by integrating the color burst parts of a signal which is obtained by subtracting a digital value corresponding to the pedestal level from a digital video signal and integrating color burst parts to apply DA-conversion.

CONSTITUTION: The level of a digital video signal DVS11 is detected at a detecting circuit 281 and sets an RS flip flop (FF) 257. The Q-output of an FF275 is introduced to the B-input of a 10-bit data selector 269. At this time, the B- input data of the data selector 269 are already inputted from the MSB side by an encoder after the data are converted into "1111111000". The output 270 of the data selector 269 and the 12-bit output of a latch 272 are made coincide with each other in the LSB and the difference between the outputs is obtained by a subtracter 271. This difference signal is written in the latch 272 at the output timing of the Q3 of a shift register 253. The output 20 of the latch 272 is supplied to a pedestal clamping circuit as a clamping voltage and, as a result, a stable clamping voltage is obtained.


Inventors:
KUDOU YUKINORI
SUZUKI SUSUMU
Application Number:
JP13226782A
Publication Date:
February 07, 1984
Filing Date:
July 30, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H04N5/16; H04N9/00; H04N9/455; (IPC1-7): H04N5/16; H04N9/02
Attorney, Agent or Firm:
Takehiko Suzue