Title:
SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE
Document Type and Number:
Japanese Patent JPS6066828
Kind Code:
A
Abstract:
PURPOSE:To improve the workability in the assembling step of an IC by shortening inside pins as compared with outside pins of external lead pins of a plurality of rows. CONSTITUTION:Even if the angle of the end of a bonding tool is not particularly reduced since inside pins 6b are shorter than outside pins 6a, wirings 5 can be performed without contacting the tool with the outside pins. Accordingly, a decrease in the bonding workability due to the reduction in the thickness of the end of the tool can be avoided, thereby preventing the increase in the size of a package 1.
Inventors:
NISHIMURA TAKAHISA
Application Number:
JP17543583A
Publication Date:
April 17, 1985
Filing Date:
September 22, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L23/50; H01L21/60; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Uchihara Shin