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Title:
LEVEL DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS59186406
Kind Code:
A
Abstract:

PURPOSE: To detect levels of many power source circuits, etc., securely at a high speed by providing plural current mirror circuits connected between plural reference power sources and a constant current source, and turning off the current mirror circuits when an input signal exceeds the reference level of the power sources and generating a detection signal.

CONSTITUTION: When the input signal from the side of a connection point P exceeds a reference voltage ±V1, a TRQ10 or TRQ11 turns off and the voltage of a resistor R45 drops to a zero level. Similarly, when the input signal exceeds a reference voltage ±V2, the voltage of a resistor R46 goes down to the zero level. Namely, when the level of the input signal is within the reference range, high-level control signals SCA and SCB appear at the collector sides of TRs Q10 and Q12, but when the level of the input signal exceeds the reference voltages, the level is inverted and low-level control signals SCA and SCB appear at the collector sides of the TRs Q10 and Q12. Namely, current mirror circuits 10∼ 13 operate as gate circuits and operate as original current mirror circuits when the input signal is within the reference level range.


Inventors:
OOSAWA MITSUO
Application Number:
JP6129883A
Publication Date:
October 23, 1984
Filing Date:
April 07, 1983
Export Citation:
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Assignee:
SONY CORP
International Classes:
G01R19/00; G01R19/165; H03F1/02; (IPC1-7): H03F1/02
Domestic Patent References:
JPS53119647A1978-10-19
Attorney, Agent or Firm:
Sada Ito (1 person outside)



 
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