PURPOSE: To prevent useless access request, by storing and comparing respective memory addresses and controlling the access request to a main memory during the data transfer from the main memory to a cash memory and during the waiting period of main memory access.

CONSTITUTION: During the execution of data transfer, a comparator 4 is made enable via a cash memory 2, and a block address during data transfer of a block address register 3 and a block address of virtual processors 1-0, 1-1... requesting readout via a bus line 100 are compared. When the output of the comparator 4 is inverted to 1 due to coincidence, the issue of readout request from the processors 1-0, 1-1... via a logical sum circuit 7 and an inhibition gate 9 is inhibited. Similarly, when the block address of the processors 1-0, 1-1... making readout request and that of stack address registers 5-0, 5-1... during waiting for main memory access are coincident with each other, the issue of readout request is inhibited, allowing to prevent useless main memory access request and to improve the processing ability.