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Title:
INTEGRATED THIN FILM ELEMENT
Document Type and Number:
Japanese Patent JPS5853859
Kind Code:
A
Abstract:

PURPOSE: To obtain an integrated thin film element comprising a three-dimensional circuit by forming the first element having electrode on the single surface of thin film layer and the second element having electrode opposing thereto on the other surface and by connecting them with the conductive layer in the thin film.

CONSTITUTION: An N type amorphous Si (a-)13 and a gate oxide film 14 are laminated selectively on an i-type a-Si 12 on a substrate 11 and not-diffusible Mo 15 and diffusible Al 16 are also stacked on said a-Si. The Mo is etched in order to form the gate electrode and succeedingly the Al 16 is patterned. The i-type a-Si 17 and N type a-Si 18 are stacked and the source, drain electrodes are formed by the layer 18. At the time of this stacking, the substrate temperature is kept lower than that when the layers 12, 13 are formed in order to prevent isolation of H2 from the layers 12 and 13. As a result, the aluninum 16 diffused regions 19 and 20 are formed, the second gate oxide film 21 is formed selectively, the metal 22 is evaporated and thereby the electrode and wiring are formed, thus completing an integrated thin film element.


Inventors:
ISHIHARA SHINICHIROU
Application Number:
JP15273481A
Publication Date:
March 30, 1983
Filing Date:
September 26, 1981
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L27/00; H01L21/8242; H01L27/01; H01L27/108; H01L27/12; (IPC1-7): H01L27/01; H01L27/10
Domestic Patent References:
JPS5080788A1975-07-01
JPS5130485A1976-03-15
Attorney, Agent or Firm:
Toshio Nakao