PURPOSE: To perform subminiaturization, high integration, and an increase in capacity by providing the 1st FET of the 1st conduction type, 2nd FET of the 2nd conduction type, 3rd FET, capacitance between the gate of the 3rd FET and the 2nd electrode, a digit line, and an address line.

CONSTITUTION: The P area 107 of a P channel MOST and the P gate 109 of an N channel JFET float electrically to form a charge storage area, and capacitance 113 connected to it is charged and discharged to store binary information. For writing, an address line 119 connecting with the gates 101 and 105 of two N channel and P channel MOSTs, and a digit line 118 connecting with the JFET are held at a prescribed voltage to turn on the P channel MOST. For reading, the digit line 118 is connected to a sense amplifier and the address line 119 is held at a prescribed voltage to turn on or off the JFET. Thus, a memory which is integrated high and subminiaturized easily and has large capacity is obtained.