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Title:
CLAMP CIRCUIT
Document Type and Number:
Japanese Patent JPS60134565
Kind Code:
A
Abstract:

PURPOSE: To attain an accurate clamp operation based on a sample-and-hold value by providing a limiter circuit to control the input amplitude to an sample- and-hold circuit.

CONSTITUTION: A burst flag pulse BF goes to a high level at a video section of video signal shown in Fig. at an input point, a transistor (TR) Q18 is turned on, and a current corresponding to a current source 3 flows, then a differential amplifier 2 is turned off and sample information is stored in a capacitor C of the collector of the TRQ1. A sample-hold output at one end of the capacitor C is fed back negatively to a TRQ12 of a differential amplifier 7 constituting a DC circuit 1 via an emitter follower of TRs Q19, Q20, Q21, and the level control is attained so that the pedestal level of an input video signal and a reference voltage Vr are coincident with each other. Then the control loop is stabilized by bringing the pedestal level to the voltage Vr.


Inventors:
UTSUNOMIYA TOKITAKE
OKITSU HIROMI
FUKUSHIMA NORIYUKI
Application Number:
JP24287283A
Publication Date:
July 17, 1985
Filing Date:
December 22, 1983
Export Citation:
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Assignee:
SONY CORP
International Classes:
H04N5/18; (IPC1-7): H04N5/18
Attorney, Agent or Firm:
Tsuchiya Masaru



 
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