Title:
BUS ACCESS ERROR PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP3177794
Kind Code:
B2
Abstract:
PURPOSE: To facilitate the processing of a bus access error, caused by a CPU, and easily extend a bus which can be maintained in a hot-line state as to the system which processes the bus access error.
CONSTITUTION: If the bus access error is caused, namely, if access from the CPU l to a controlled device 3 through the bus 2 does not end normally, the controlled device 3 sends a bus error signal back to the CPU 1, which performs an exceptional process on the basis of a basic program. In this system, when the CPU 1 receives the bus error signal, the bus access error occurrence is displayed with a corresponding flag 4 and a user program side can performs an evading process in case of the bus access error occurrence.
More Like This:
Inventors:
Noriyuki Yokoshi
Kazuyuki Miura
Nobuko Hatanaka
Kazuyuki Miura
Nobuko Hatanaka
Application Number:
JP24921692A
Publication Date:
June 18, 2001
Filing Date:
September 18, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F11/00; G06F13/00; (IPC1-7): G06F11/00
Domestic Patent References:
| JP4125754A | ||||
| JP3265053A | ||||
| JP1131943A |
Attorney, Agent or Firm:
Shoji Kashiwaya (1 person outside)
Previous Patent: 容器ホルダー
Next Patent: AUTOMATIC DEVELOPING MACHINE FOR SILVER HALIDE PHOTOGRAPHIC SENSITIVE MATERIAL
Next Patent: AUTOMATIC DEVELOPING MACHINE FOR SILVER HALIDE PHOTOGRAPHIC SENSITIVE MATERIAL