To provide a transceiver module capable of preventing a collision between return outputs from an XENPAK register group 8 of PHYIC3 and from an XENPAK register group 9a of DCU at the time of accessing the XENPAK resister group from a host 4 and besides of eliminating a register contents mismatch resulting from generation of errors of a high-speed system detected only in the PHYIC3 and low-speed system detected only in the DCU2.

The transceiver module is equipped with the PHYIC3 including the XENPAK register group 8 containing a LASI_Status register, the DCU2 including the XENPAK register group 9a emulated by the XENPAK register group 8, and an operation mode in which while the DCU2 emulats a structure and function of the XENPAK register group 8, the PHYIC3 outputs no reply to access to the XENPAK register group 8 from a host 4.