PURPOSE: To increase the signicance of data while shortening the latency time of data transfer with high transfer priority as much as possible, by providing a clock phase converting circuit to a subchannel controller with high transfer priority.

CONSTITUTION: A subchannel (SCH) controller A1 has higher transfer priority than an SCH controller B5, and the controller 1 is provided with a clock (CK) phase converting circuit 15, which converts the phase of a synchronizing CK by 180°. For example, a transfer request B is transferred from the controller 5 and a transfer request A4 is also transferred from the controller 1 in succession to a 180° phase difference from a reference CK. In a channel controller 9, th requests A4 and B8 are sampled by a transfer request detecting circuit 11 with a reference CK from a reference CK generating circuit 10 and their detection signals are transferred to a priority level controller 12. As a result, the detection signals of both the requests A4 and B8 are transferred to the circuit 12 simultaneously, so a transfer command A13 is transferred to the controller 1 according to the transfer priority to perform data transfer between the controller 1 and 9.