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Patent Searching and Data


Title:
TRANSISTOR CIRCUIT WITH ELECTROSTATIC EFFECT
Document Type and Number:
Japanese Patent JPH04211517
Kind Code:
A
Abstract:

PURPOSE: To obtain a push-pull circuit with high load driving ability by making the gate width of two FETs connected in series, different from each other, by a prescribed value.

CONSTITUTION: A push-pull circuit is formed by FETs Q11 and Q12 connected in series on a same semiconductor circuit substrate, and an inverter formed by a depression type transistor(TR) and an enhancement type TR connected in series is connected at the prestage of the FETs Q11 and Q12. The electric charge accumulated in the capacitor of load is discharged when the FET Q12 is turned on corresponding to the output of the inverter; and a capacitor C is charged via the FET Q11 a when the FET Q11 is turned on. Since a sate width Wg1 of the FET Q11 making charge current to flow to the load is set larger than a gate width Wg1 of the discharging FET Q12 and drain current at the rising time can be increased, the push-pull circuit with improved driving ability can be obtained.


Inventors:
KATAOKA SHIGERU
Application Number:
JP4696491A
Publication Date:
August 03, 1992
Filing Date:
March 12, 1991
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03K19/0952; H03K19/017; (IPC1-7): H03K19/0952
Attorney, Agent or Firm:
Kazuo Sato (3 others)