Title:
トランジスタ装置、集積回路及び製造方法
Document Type and Number:
Japanese Patent JP5714722
Kind Code:
B2
Abstract:
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibit reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
Inventors:
Grass, Glen A.
Mercy, Anand S.
Mercy, Anand S.
Application Number:
JP2013546324A
Publication Date:
May 07, 2015
Filing Date:
December 20, 2011
Export Citation:
Assignee:
Intel Corporation
International Classes:
H01L21/336; B82Y30/00; B82Y40/00; H01L21/28; H01L29/06; H01L29/41; H01L29/78; H01L29/786
Domestic Patent References:
| JP2007214481A | ||||
| JP2009514248A | ||||
| JP2010519734A | ||||
| JP2007165665A | ||||
| JP2009200090A | ||||
| JP2010171337A | ||||
| JP2012510720A |
Foreign References:
| US20070187767 | ||||
| US20080054347 | ||||
| WO2010068530A1 | ||||
| WO2007053381A1 | ||||
| US20080197412 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Naoki Fujimura
Tadahiko Ito
Shinsuke Onuki
Naoki Fujimura