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Title:
TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Document Type and Number:
Japanese Patent JP2003234472
Kind Code:
A
Abstract:

To sharply reduce the diffusion of germanium to a gate dielectric.

A metal oxide semiconductor (MOS) transistor for an integrated circuit includes a gate area and a gate dielectric layer 32 positioned in the gate area. In this gate dielectric layer 32, germanium diffusing from an epitaxial Si1-xGex alloy layer 18 to the gate dielectric layer 32 is substantially made absent. This method comprises a process for building up a dummy displacement gate, a process for carrying out high temperature treatment to elements, a process for removing a dummy gate 28A, and a process for building-up dielectric materials to be turned into the gate dielectric layer 32 and final gate materials in the gate area. Thus, the dielectric materials to be turned into the gate dielectric layer 32 are built up after the high temperature treatment is carried out to the elements, and the quantity of germanium diffusing to the dielectric materials is ignorable.


Inventors:
MA YANJUN
TWEET DOUGLAS J
EVANS DAVID RUSSELL
Application Number:
JP2002369365A
Publication Date:
August 22, 2003
Filing Date:
December 20, 2002
Export Citation:
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Assignee:
SHARP KK
International Classes:
H01L21/28; H01L21/336; H01L21/337; H01L29/423; H01L29/49; H01L29/78; H01L29/80; (IPC1-7): H01L29/78; H01L21/28; H01L21/336; H01L29/423; H01L29/49
Attorney, Agent or Firm:
Shusaku Yamamoto (2 outside)