Title:
TRANSISTOR PIN ALIGNING METHOD
Document Type and Number:
Japanese Patent JPS5285466
Kind Code:
A
Abstract:
PURPOSE: To improve positioning accuracy and make possible mechanization of pin alignment by selecting rail spacing also with transistors of narrow pin-topin spacings.
Inventors:
MORI MASATAKA
Application Number:
JP186176A
Publication Date:
July 15, 1977
Filing Date:
January 09, 1976
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H05K13/04; H01L23/48; H05K5/00; (IPC1-7): H01L23/48; H05K5/00
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