TRANSISTOR OF STATIC ELECTRICITY PROTECTIVE CIRCUIT AND MANUFACTURE OF THE SAME

Japanese Patent JP3516565

B2

PROBLEM TO BE SOLVED: To prevent a junction leak current to improve the ESD characteristic when an ESD voltage is applied by superimposed arrangement of at least one region of the first and second high concentration impurity regions within an operation region edge.
SOLUTION: A metal gate N-channel field transistor comprises a well 71 formed on a silicon substrate, an element isolation insulating film 72 formed in this well, an LDD low concentration impurity region 73, an N+ drain high concentration impurity diffused region 74 formed in the region 73, an N- source high concentration impurity diffused region 741 formed in the region 74, an insulating film 75 formed on the element isolation insulting film 72 and LDD low concentration impurity region 7 and a metal gate electrode 76 formed on the LDD low concentration impurity region 73 and insulating film 75. The N+ drain high concentration impurity diffused region 74 is arranged to provide the superimposed area with the operation region of at least 0.1μm. Thereby, the junction leak current when the ESD voltage is applied can be minimized and the ESD characteristic can also be improved.

Tei, Zaikan
Boku, Konu

JP34614496A

April 05, 2004

December 25, 1996

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HYUNDAI ELECTRON IND CO LTD

H01L21/336; H01L21/822; H01L27/02; H01L21/331; H01L27/04; H01L27/06; H01L29/06; H01L29/73; H01L29/78; H01L21/768; (IPC1-7): H01L27/06; H01L21/822; H01L27/04; H01L29/78

JPH0372666A
JPH0235778A
JPH02177366A
JPH03101269A
JPH0513757A
JPH0786585A

長谷川 芳樹 （外２名）

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