Title:
TRANSISTOR STRUCTURE
Document Type and Number:
Japanese Patent JPS6170758
Kind Code:
A
Abstract:
Vertical transistor structure with an epitaxially applied layer of the second conduction type on a semiconductor substrate of the first conduction type, in which a tray is formed by insulating walls of the first conduction type extending into the semiconductor substrate. A first highly doped buried layer of the second conduction type in which a second buried layer of the first conduction type extending into the epitaxial layer of the first conduction type is embedded insulated from the semiconductor substrate. Three doped zones of which one, of the second conduction type, is provided for the base terminal and one of the first conduction type for the emitter and collector terminal, and a zone connecting the collector terminal zone and the second buried layer, of the first conduction type, where these regions form the collector. The emitter zone and the collector terminal zone are arranged above opposite end regions of the second buried layer.
Inventors:
HERUBERUTO EFU ROROFU
Application Number:
JP19369585A
Publication Date:
April 11, 1986
Filing Date:
September 02, 1985
Export Citation:
Assignee:
SIEMENS AG
International Classes:
H01L29/73; H01L21/331; H01L21/74; H01L21/761; H01L29/08; H01L29/732; (IPC1-7): H01L29/72
Domestic Patent References:
| JPS5260078A | 1977-05-18 | |||
| JP46008501A |
Attorney, Agent or Firm:
Tomimura Kiyoshi
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