PURPOSE: To increase the operation speed by providing first and second data buffer circuits, selecting these circuits to read out stored parallel data and converting it to a serial data.

CONSTITUTION: An address control buffer circuit 1 including a first end bit register which performs the read operation synchronously with a first data register 11A and a data buffer circuit 2 including a second end bit register 13 which performs the read operation synchronously with a first data register 11B are provided. A parallel/serial converting circuit 5 or the like is provided which successively converts parallel data read out from circuits 1 and 2 to serial data DTS in accordance with a flag synchronizing signal FS to send this data DTS and outputs a read signal RD. Thus, plural frames are continuously transmitted without issuing a transmission request to a host system at each time of one frame, and the operation speed is increased and the execution efficiency of the host system is improved.