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Title:
TRANSMISSION LINE IMPEDANCE MATCHING CIRCUIT
Document Type and Number:
Japanese Patent JP2005286622
Kind Code:
A
Abstract:

To provide a transmission line impedance matching circuit in which matching of line impedance is realized in a simple manner in a short period of time.

A voltage detection section 11 outputs a positive detection result signal Kp when a difference between a peak level of an overshoot of an output voltage and a high level of a digital signal or a difference between a peak level of an undershoot of the output voltage and the high level of the digital signal exceeds a maximum operating range. Further, the voltage detection section 11 outputs a negative detection result signal Kn when a difference between a level of the output voltage at a leading part and the high level of the digital signal is less than a minimum operating range if the output voltage does not reach the high level or when a difference between a level of the output voltage at a trailing part and the low level of the digital signal is less than a minimum operating range if the output voltage does not reach the low level. A control section 12 outputs a control value signal Cp for controlling the resistance of a variable resistor section 13 increasingly when receiving the positive detection result signal and outputs a control value signal Cn for controlling the resistance of the variable resistor section 13 decreasingly when receiving the negative detection result signal. The variable resistor section 13 uses the control value signal C to linearly change the resistance.


Inventors:
ARAIYA TAKAHISA
Application Number:
JP2004096562A
Publication Date:
October 13, 2005
Filing Date:
March 29, 2004
Export Citation:
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Assignee:
NEC ENGINEERING LTD
International Classes:
G06F3/00; H03H7/38; H03H7/40; H04L25/02; (IPC1-7): H04L25/02; G06F3/00; H03H7/38; H03H7/40
Attorney, Agent or Firm:
Katsuharu Sato



 
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