PURPOSE: To reduce bit number when data with the same positive/negative range width are quantized and sent by adding a sign bit to the end of data and sending specific quantization data in a shorter bit length than an original bit length.

CONSTITUTION: Data read from a memory 1 storing transmission data with a data clock outputted from an n/(n-1)-adic counter 7 are fed to a zero detector 3 and a parallel load shift register 5. The parallel load shift register 5 sends its output so that a positive/negative sign bit is sent finally by using a prescribed bit clock. When the outputted data are zero, the zero detector 3 detects the data and the n/(n-1)-adic counter 7 acts like an (n-1)-adic counter when zero is detected in the bit clock and acts like an n-adic counter in other cases and outputs a data clock to the memory 1 and the parallel load shift register 5. That is, when quantization data are zero, the positive/negative sign bit being the tail end one-bit is not sent.