To provide a compensation circuit capable of suppressing current consumption without largely increasing the scale of a circuit.

A power detection part 11 detects an RF signal divided by a directional coupler 4 and outputs a transmission level to an address generation part 10 as a certain DC voltage value V1. A power calculator 6 calculates the instantaneous power of a base band signal and outputs the calculated value to the address generation part 10 as a certain AC voltage value v2. The address generation part 10 determines the address of data to be outputted from a 1st memory 7 on the basis of the value of (DC voltage value V1+AC voltage value v2). The 1st memory 7 stores compensation data as a table and outputs data included in a specified address to a predistortion type linearizer 2. A CPU 9 transfers a compensation data table concerned from a 2nd memory 8 to the 1st memory 7 in accordance with a change in an ambient temperature or transmission frequency.