PURPOSE: To test the circuit efficiently and to realize the test unit of 64kb/s or over by providing a means generating a test signal predetermined for a transmission interface section or a reception interface section and a means inserting the test signal to a predetermined signal position.
CONSTITUTION: This device is provided with a means 12 generating a test signal predetermined for transmission interface sections 33, 31 or reception interface sections 31, 33 and a means 14 inserting the test signal to a predetermined signal position. That is, the transmission interface sections 33, 31 and the reception interface sections 31, 33 are respectively provided to an outgoing line and an incoming line being high speed digital lines, and the processing such as multiplex conversion and exchange being time slot conversion is implemented between the reception interface sections 31 or 33 and the transmission interface sections 33 or 31. Thus, the test function is economized and made highly efficient and the test unit of 64kb/s or over is realized.
MORINO SHIGEO
JPS56119546A | 1981-09-19 | |||
JPS5691549A | 1981-07-24 |