Title:
TRAY FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND LEAD CORRECTING METHOD WITH THE TRAY
Document Type and Number:
Japanese Patent JP3202716
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To eliminate or reduce an inspection over a total number of devices during a manufacturing stage of a semiconductor integrated circuit device, adding of a lead correcting function or an inspection over a total number of devices when the devices are actually mounted, thereby reducing a cost caused by poor shape of lead at the manufacturing stage or at the actual mounting stage.
SOLUTION: This tray for semiconductor integrated circuit device is made such that a semiconductor integrated circuit device 4 is stored between a first tray structure 2 and a second tray structure 3. In this case, the first tray structure 2 and the second tray structure 3 are provided with lead correcting function segments 7, 8 formed to correct the leads 6 at locations where the leads 6 of the semiconductor integrated circuit device 4 are positioned under a state in which they are overlapped to each other while the semiconductor integrated circuit device 4 is stored therein.
Inventors:
Miharu Nunokawa
Application Number:
JP3117199A
Publication Date:
August 27, 2001
Filing Date:
February 09, 1999
Export Citation:
Assignee:
Yamagata NEC Corporation
International Classes:
B65D85/86; H01L23/00; (IPC1-7): B65D85/86; H01L23/00
Domestic Patent References:
| JP8146083A |
Attorney, Agent or Firm:
Yoshiyuki Iwasa
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