To provide a triac controller which can suppress the deviation of drive timing of a triac by a simple configuration, and can achieve stable operation of a load.
A counter (101b) repeats count operation from an initial count "1" for each AC voltage rising zero-cross point detected by a zero-cross detection unit (11). When the count of the counter (101b) reaches the end count "20" before the AC voltage rising zero-cross point, a triac control unit (101a) turns a gate drive signal on for a predetermined period, and when the count of the counter (101b) becomes the initial count "1" immediately after the rising zero-cross point, turns a gate drive signal on for a predetermined period. When the count of the counter (101b) becomes an intermediate count "10", the triac control unit (101a) turns a gate drive signal on for a predetermined period.
UCHIYAMA MASAYA
JPH10214687A | 1998-08-11 | |||
JPS6311061A | 1988-01-18 | |||
JPH0473523A | 1992-03-09 |
Mitsuo Tanaka
Yukinori Nakakura
Etsuko Isoe
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