PURPOSE: To prevent an excess trigger signal from being generated when the generating timing of the trigger signal is desired to be delayed by using an AND circuit receiving a mask request signal and the trigger signal so as to mask a first trigger signal from a counter.

CONSTITUTION: An H level is outputted from the noninverting output terminal Q of an FF4 every time when a clock is inputted to the FF4 through a data bus 8 and fed to the data input terminal D of an FF5. When a trigger signal 10 is fed from a counter 3 to the clock input terminal CK of the FF5, an L level is outputted from an inverting output terminal Q. Then an L level signal is outputted from an AND circuit 6 to mask the 1st trigger signal 10 from the counter 3. Moreover, the L level signal from the FF5 is fed to the reset input terminal R of the FF4 to reset the FF4, an L level is outputted from the noninverting output terminal Q and inputted to the data input terminal D of the FF5. Thus, the H level signal is outputted from the inverting output terminal Q of the FF5, an H level trigger signal 12 is outputted from the circuit 6 and a 2nd shot trigger pulse signal 10 is outputted without being masked.