Title:
TRIPLE SEQUENCE CIRCUIT
Document Type and Number:
Japanese Patent JPS61160101
Kind Code:
A
Abstract:
PURPOSE:To avoid the influence of a single failure generated in any one sequence of a triple self-holding circuit by constituting the self-holding signal of each self-holding circuit of a 2/3 logical signal between the output signals of corresponding other two self-holding circuits and the output signal of the self-holding circuit concerned. CONSTITUTION:When it is supposed that an optional one power source, e.g. 11a, out of power sources 11a-11c is braked during the excitement of all relays 11a-11c, relays 14a, 15a are unexcited, but the states of other relays and an output signal to a controlled system 30 are not changed. When the power source 11a is restored, relay contacts 14b, 14c are continuously closed, so that the relay 15a is excited and a sequence circuit 10a is restored to the original state simultaneously with the restoration of the power source 11a without the execution of any operation. When the power source 11b or 11c is braked, the same rule is applied.
Inventors:
SAKAKIBARA SHINJI
Application Number:
JP33185A
Publication Date:
July 19, 1986
Filing Date:
January 08, 1985
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G05B9/03; (IPC1-7): G05B9/03
Attorney, Agent or Firm:
Noriyuki Noriyuki
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