Title:
TWO-INPUT LATCH CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3231423
Kind Code:
B2
Abstract:
PURPOSE: To provide a two-input latch circuit device which reduces the parasitic capacity in the signal transfer route from an input terminal to an output terminal to-shorten the delay time by specifying the arrangement of switch circuits.
CONSTITUTION: A fourth switch circuit 1b has one end connected on the way of the circuit connecting a first switch circuit 1d and a second switch circuit 1c and has the other end connected to a second data input terminal D2 for data input. That is, the contact capacity of two switch circuits 1a and 1d and the input terminal capacity of a buffer circuit 2 are connected as the parasitic capacity to an output terminal Q, and the parasitic capacity is reduced. Consequently, the delay time from an input terminal D1 to the output terminal Q is shortened. Or, the output terminal may be connected on the way of the circuit connecting a third switch circuit which receives data from a first input terminal and a second switch circuit connected in series to the third switch circuit.
Inventors:
Hidefumi Maeno
Application Number:
JP28223092A
Publication Date:
November 19, 2001
Filing Date:
September 29, 1992
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03K3/356; H03K3/037; H03K3/286; (IPC1-7): H03K3/356; H03K3/037; H03K3/286
Attorney, Agent or Firm:
Hiroaki Tazawa (2 outside)