PURPOSE: To achieve a wide frequency range and an intermediate temperature characteristic by providing input and output of opposite phase data of each basic cell so that they are formed by a first and second input terminals or output terminals, being properly connected conductively, being supplied with a latch clock, and being connected to the latch clock line.

CONSTITUTION: Opposite phase data inputs of each basic cell Z1-Z2n are formed by a first and a second input terminals, and are connected with emitters of specified transistors respectively, while opposite phase data outputs of each basic cell Z1-Z2n are formed by a first and a second output terminals, and are connected with collectors of specified transistors respectively. Further, each shift register stage includes latches 11-1n so the data outputs and is provided with the basic cells Z1-Z2n and an output stage 1a, and is connected with a latch clock line by being supplied with a latch clock L. Thus, the clock shift register is provided with a wide frequency range and an intermediate temperature characteristic and can be used as a data word during an optional period.