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Title:
TWO-PORT MEMORY IC
Document Type and Number:
Japanese Patent JPS6379289
Kind Code:
A
Abstract:

PURPOSE: To realize a sequential output of a data block without any external circuit by providing an index register, an address register and a word counter in a memory IC and transferring its initial value from a memory.

CONSTITUTION: An address register 32 is connected to a data bus from a memory 11 to an output port B, the head address of an index area next to the index area is transferred to the index register 31, and the head address in the index area is transferred nearly at the same time. Until the newest signal is inputted, the register 32 is incremented by a prescribed interval synchronously with the clock input. Then the word counter 33 is decremented by a prescribed interval synchronously with the clock input, and when the content reaches zero, an up-date signal is outputted to switch a selector 37. Each counter is provided in this way and the initial value is transferred from the memory 11 to realize the sequential output of the data block without receiving it from any external circuit.


Inventors:
FUKUSHIMA YUTAKA
Application Number:
JP22678686A
Publication Date:
April 09, 1988
Filing Date:
September 24, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C7/00; (IPC1-7): G11C7/00
Attorney, Agent or Firm:
Uchihara Shin



 
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