Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JP3171289
Kind Code:
B2
Abstract:
PURPOSE: To shorten the time required to erase the address conversion buffers of a virtual storage type information processor consisting of plural processors that share main storage.
CONSTITUTION: When an erasure instruction for the address conversion buffer appears, an instruction analysis part 11 or 21 instructs erasure control parts 13 and 23 to erase the address conversion buffers, and starts processing a next instruction after the processing of the instruction ends. The erasure control parts 13 and 23 indicates the erasure of address conversion information to the address conversion buffers 4 and 24 and indicates the index stop of the address conversion buffers to index control parts 12 and 22 during the erasure.
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Inventors:
Katsuaki Uchibori
Application Number:
JP33590493A
Publication Date:
May 28, 2001
Filing Date:
December 28, 1993
Export Citation:
Assignee:
NEC
International Classes:
G06F15/16; G06F12/10; G06F15/163; G06F15/177; (IPC1-7): G06F12/10; G06F15/16
Domestic Patent References:
| JP5189318A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)