PURPOSE: To obtain an up-down counter whose count is unchanged by switching the count operation executed by the up-down counter circuit before a switching signal is inputted even when up-count or down-count is switched on the way of count.

CONSTITUTION: The up-counter is provided with a control signal generating circuit 60 generating a 1st control signal A and a 2nd control signal B based on a 2nd clock signal CLK2 and a switching signal U/D. Furthermore, 2nd, 3rd gate circuits 81-84 inverting outputs of delay flip-flop circuits D-FF 51-54 of each stage with the 1st control signal A and plural multiplexers 91-94 selecting an output of the flip-flop circuits D-FF 51-54 of each stage based on the 2nd control signal B are provided, then even when up-count and down- count are selected on the way of the count, the accurate up-down counter circuit in which the count is not deviated is obtained. Thus, a means correcting the count or the like is not required.