PURPOSE: To enable an up-down counter to make up- and down-counting at an arbitrary pitch by connecting the outputs of latch circuits to the inputs of full adders and, at the same time, the outputs of the full adders to the inputs of the latch circuits.
CONSTITUTION: When latch circuits 21-24 are reset with a reset signal 122, all of the output signals of the circuits 21-24 become 'L' and the outputs 131-134 of full adders 11-14 respectively become the sums of the signals 111-114 and signals 101-104. When a clock 121 is inputted thereafter, the outputs 131-134 are latched by means of the latch circuits and outputted as the signals 111-114 which change by the value set at every clock by the signals 101-104. Therefore, this up-down counter can make up and down-counting at an arbitrary pitch. The (n) represents a prescribed bit number.
JPS61189731A | 1986-08-23 | |||
JPS6318722A | 1988-01-26 |