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Title:
VARIABLE CLOCK GENERATION CIRCUIT AND SERVO DRIVE DEVICE PROVIDED WITH THE SAME
Document Type and Number:
Japanese Patent JP2008123402
Kind Code:
A
Abstract:

To provide a variable clock generation circuit that generates a dividing clock at an arbitrary duty ratio while generating an arbitrary dividing clock so as to dynamically change a dividing frequency and a duty ratio of the dividing clock, and to provide a servo drive device provided with the same.

The variable clock generation circuit includes: a dividing decoder 11, which is composed of an idle-state decoding part 110 for generating an idle state that stops the dividing clock S4 and divided state decoding parts 111, 112, 113, and 11N so as to generate a next state S6 on the basis of an inputted frequency selection signal S3 and a state S5; and a state-storage flip-flop 12 for generating a new state S5 while latching the next state S6 with an input clock S1. One arbitrary bit in the state S5 being output of the state-storage flip-flop 12 is made as the dividing clock S4.


Inventors:
Kashiwagi, Yoshitaka
Application Number:
JP2006000308795
Publication Date:
May 29, 2008
Filing Date:
November 15, 2006
Export Citation:
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Assignee:
YASKAWA ELECTRIC CORP
International Classes:
G06F1/08; H03K23/64