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Title:
VARIABLE DELAY CIRCUIT, ITS SETTING METHOD AND SEMICONDUCTOR TEST DEVICE
Document Type and Number:
Japanese Patent JP2002076860
Kind Code:
A
Abstract:

To avoid the effect caused by the sink phenomenon in the case of measuring the delay time of a variable delay circuit.

A circuit adopting the setting method of this invention is provided with a memory that stores the correlation between the combination of delay sections causing a delay time among delay sections 1a-1n and the delay time and is further provided with an offset section 10 that is connected in series with the delay sections and produces a delay time to shift the period of self- running loop oscillation to a period other than that in the vicinity of a multiple period when the period of the self-running loop oscillation is close to the multiple period of the operating period of surrounding electric circuits in the case of measuring the delay time by the combination of the delay sections in the self-running loop oscillation state in order to set the correlation to this memory.


Inventors:
OCHIAI KATSUMI
Application Number:
JP2000264025A
Publication Date:
March 15, 2002
Filing Date:
August 31, 2000
Export Citation:
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Assignee:
ADVANTEST CORP
International Classes:
G01R31/319; H03K5/14; G01R31/28; (IPC1-7): H03K5/14; G01R31/28; G01R31/319
Attorney, Agent or Firm:
Kihei Watanabe