Title:
VARIABLE DELAY CIRCUIT
Document Type and Number:
Japanese Patent JP3045092
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a circuit suitable for high speed operation environment by avoiding deterioration due to noise from being given to a signal waveform and to provide the circuit with low power consumption and a high degree of circuit integration where the number of variable stages is increased and a large delay time is obtained.
SOLUTION: The circuit is so configured that the length of branched lines in signal lines is very short regardless of any setting of a variable stage number. More concretely, a plurality of delay sections (DL1-DL3) are connected in series via transfer gates (PT1-PT3) each consisting of a P-channel MOS TR, and a main input terminal N1 and output terminals of each delay section are connected to a main output terminal NO via transfer gates (NT1-NT4) each consisting of an N-channel MOS TR.
Inventors:
Yasuaki Fukuma
Application Number:
JP4241297A
Publication Date:
May 22, 2000
Filing Date:
February 26, 1997
Export Citation:
Assignee:
NEC
International Classes:
H03K5/13; (IPC1-7): H03K5/13
Domestic Patent References:
| JP6350416A | ||||
| JP550834U |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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