PURPOSE: To obtain the variable delay circuit in which the maximum operation possible frequency is independent of the range of delay bit number, by cascade connection of fundamental constituent circuits consisting of the common connection of the first and second delay circuits for the input side and the connection of the selection circuits for the output side.
CONSTITUTION: The fundamental circuit is constituted with the common connection of the input of the shift register SR2 of the first delay circuit and SR16 of the second delay circuit, and the connection of the output to one input of the selection circuit 7 respectively. Similarly, the fundamental circuits constituted with Sr17, 4 and SR5, 18 and SR6, 19 and the selection circuits 8, 9, 10 are cascade-connected. Each selection circuit is controlled with the control signals 12 to 15 and SR is controlled with the closk signal from the terminal 11. The delay time of the selection circuit is the sum of the time tpd1 from the output of SR to the selection circuit and the time tpd2 from the output to the next SR, and it is constant. This is independently of the combination of the control signals 12 to 15, one selection circuit is in the flow of one signal, and the delay time of the selection circuit is not added. Accordingly, the number of maximum operation possible frequency is independent of the range of delay bit to ensure the high speed operation.
KIMURA TADAKATSU
KIKUCHI KOUICHI
NIPPON ELECTRIC CO
| JP40012922A |