To provide a variable delay element inspection circuit which can simply and easily detect a failure when a wiring route in a variable delay element generates 0 degenerate failure or 1 degenerate failure.

This variable delay element inspection circuit is provided with a first delay element 3 connected with the output end of a first multiplexer 1, a second delay element 4 connected with the output end of a second multiplexer 2, an OR circuit 5 connected with the output ends of the first and the second delay elements 3, 4, and a control circuit 6 controlling the first and the second multiplexers 1, 2. A test mode signal TEST, a first and a second logic forced set signals D0, D1, and a selection signal S are inputted in the control circuit 6. By variously changing the logic of the signals, the 0 degenerate failure and the 1 degenerate failure in the wiring routes in the variable delay elements are detected.