PURPOSE: To obtain a variable frequency divider circuit not incurring much trouble by receiving a value A set by an m-bit binary number and varying the frequency divider ratio while varying the setting value A.

CONSTITUTION: Number of output terminals of a decoder 1 receiving the value A set in m-bit binary number, let (m) be 3 and the setting value A be 2, is 8, the loworder two-terminal of the 8 sets of output terminals goes to a level 1 through a bit width setting means 2 and the signals whose level is at logical 1 at the two terminals are given to parallel signal input terminals So of an 8-bit shift register 3. The series signal output terminal So is connected to the serial signal input terminal Si to form a ring counter, then signals two of which among 8 series signals are at logical 1 are outputted repetitively and given to the input terminal of a 1/N frequency divider 4 to enable the divider at 1-level input. Thus, an output whose frequency divider ratio is (2m.N)/A=(8.N)/2 is obtained from the 1/N frequency divider 4. Thus, the variable frequency divider circuit incurring much trouble is obtained.