To provide a PLL circuit which can switch the frequency of its output signal at a high speed in short periods.

A latch circuit 2 latches parallel signals Data inputted from the outside based on a latch signal LEC and outputs the latched signals as a frequency dividing ratio setting signal DLH. A comparison counter circuit 3 outputs frequency-divided signals LD obtained by dividing the frequency of input signals and, at the same time, starts frequency dividing operations at a new frequency dividing ratio based on the signal DLH inputted from the latch circuit 2 based on the output of the frequency-divided signals LD. A timing control circuit 21 generates the latch signal LEC based on an original latch signal LE inputted from the outside and the frequency-divided signals LD and, at the same time, stops the output of the latch signal LEC during the transition period from the state where the comparison counter circuit 3 outputs the frequency-divided signals LD to the termination of the output.